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Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (see
Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)
upon power-up and b) after the receipt of the stop bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire
part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Device Power Up And Power Down Recommendation
POWER UP: It is recommended to power up from 0V to full VCC in less than 1ms and then
hold for at least 100μs at full VCC level before first operation.
POWER DOWN: It is recommended to power down from full VCC to 0V in less than 1ms and
then hold at 0V for at least 0.5s before power up. It is not recommended to VCC power down
to non-zero volt and then slowly go to zero volt.
6
AT24C1024
1471O–SEEPR–3/07
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